Semiconductor memory device and manufacturing method thereof

ABSTRACT

A method for manufacturing a semiconductor memory device includes forming a magnetic tunnel junction layer on a lower electrode, forming a spacer having an annular shape on the magnetic tunnel junction layer, forming upper electrodes on both sidewall surfaces of the annular shaped spacer, removing the spacer, and etching the magnetic tunnel junction layer by using the upper electrodes as an etch mask.

CROSS-REFERENCE(S) TO RELATED APPLICATIONS

The present application claims priority of Korean Patent Application No.10-2011-0026277, filed on Mar. 24, 2011, which is incorporated herein byreference in its entirety.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor memory device and amanufacturing method thereof, and more particularly to amagneto-resistive random access memory (MRAM) and a manufacturing methodthereof.

Semiconductor memory devices include Dynamic Random Access Memory (DRAM)devices. However, the DRAM devices have limitations such as being scaleddown and maintaining a capacitance of capacitors that store data in thescale-down devices. To overcome the limitations of conventional DRAMdevices, semiconductor memory devices structures have been developed. Asone type of memory device, a Magneto-resistive Random Access Memory(MRAM) device uses the characteristics of Tunneling Magneto-Resistance(TMR), The TMR is a magneto-resistive effect that occurs in a magnetictunnel junction (MTJ).

The MRAM device is a non-volatile memory device where data is stored bymagnetic storage elements having different resistances according to amagnetic field changed by magnetic polarities of two ferromagneticplates forming the MTJ. The MTJ is a component including twoferromagnetic plates separated by an insulating layer. A firstferromagnetic plate is a pinned layer (PL) set to have a magneticpolarity, and a second ferromagnetic player is a free layer (FL) havinga polarity changed by a current passing through the layers.

When electrons passing through a first plate of the two ferromagneticplates penetrate into the insulating layer serving as a tunnelingbarrier, the probability that the electrons penetrating into theinsulating layer changes based on the polarity of a second plate of thetwo ferromagnetic plates. If the polarities of the two ferromagneticplates are parallel (the same direction), the tunneling current ismaximized. Otherwise, if the polarities of the two ferromagnetic platesare opposite, the tunneling current is minimized. The state of thetunneling current indicates what information is stored in the MTJ.

The MRAM device typically uses a Spin Transfer Torque (STT) technique towrite data therein. The STT technique uses spin-aligned (“polarized”)electrons to directly torque domains. The torque will be transferred toa nearby ferromagnetic plate, according to an effect that may modify theorientation of a ferromagnetic plate in a tunnel magnetoresistance orspin valve using a spin-polarized current. When the spin-polarizedcurrent flows into the ferromagnetic plate, if the magnetic orientationof the ferromagnetic plate is not the same as the polarity of thecurrent, the magnetic orientation is aligned to the polarity of thecurrent so that the data can be written.

In the MTJ included in the MRAM device, when electrons flow from thepinned layer to the free layer, the magnetic orientation of the freelayer is aligned with that of the pinned layer by the electrons havingspin aligned with the polarity of the pinned layer. Thus, the MTJ canstore a first type of data. Otherwise, if electrons flow from the freelayer into the pinned layer, spin accumulation occurs at boundary areasof the pinned layer and the free layer. Thus, the magnetic orientationof the free layer is oppositely aligned with that of the pinned layer sothat a second type of data can be stored in the MTJ.

SUMMARY OF THE INVENTION

An embodiment of the present invention is directed to amagneto-resistive random access memory (MRAM) device including aplurality of magnetic tunnel junctions (MTJs).

In accordance with an embodiment of the present invention, a method formanufacturing a semiconductor memory device includes forming a magnetictunnel junction layer on a lower electrode; forming a spacer having anannular shape on the magnetic tunnel junction layer; forming upperelectrodes on both sidewall surfaces of the annular shaped spacer;removing the spacer; and etching the magnetic tunnel junction layer byusing the upper electrodes as an etch mask.

In accordance with another embodiment of the present invention, asemiconductor memory device includes a plurality of magnetic tunneljunction elements configured to store data; and a transistor commonlyconnected to the plurality of magnetic tunnel junctions, wherein theplurality of magnetic tunnel junction elements includes a plurality ofconcentrically aligned magnetic tunnel junction layers and plurality ofconcentrically aligned upper electrodes over a lower electrode.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B illustrate magnetic tunnel junctions (MTJs) included ina magneto-resistive random access memory (MRAM) device in accordancewith an embodiment of the present invention.

FIGS. 2A to 2H illustrate a method for forming two MTJs in amagneto-resistive random access memory (MRAM) device in accordance withan embodiment of the present invention.

FIG. 3 illustrates an MRAM including a plurality of MTJs in accordancewith an embodiment of the present invention.

FIG. 4 illustrates the MTJ manufactured by the method shown in FIGS. 2Ato 2H.

DESCRIPTION OF SPECIFIC EMBODIMENTS

Exemplary embodiments of the present invention will be described belowin more detail with reference to the accompanying drawings. The presentinvention may, however, be embodied in different forms and should not beconstrued as being limited to the embodiments set forth herein. Rather,these embodiments are provided so that this disclosure will be thoroughand complete, and will fully convey the scope of the present inventionto those skilled in the art. Throughout the disclosure, like referencenumerals refer to like parts throughout the various figures andembodiments of the present invention.

FIGS. 1A and 1B illustrate magnetic tunnel junctions (MTJs) included ina magneto-resistive random access memory (MRAM) device in accordancewith an embodiment of the present invention.

Referring to FIGS. 1A and 1B, the magnetic tunnel junctions (MTJs)includes two magnetic layers, which serve as a lower electrode 10 and anupper electrode 30, separated by a magnetic tunnel junction layer 20,which is an insulating layer. The lower electrode 10 is a pinned layer(PL) set to a particular polarity, and the upper electrode 30 is a freelayer (FL) having a polarity that changes according to a magnetic fieldgenerated by a current. For example, if the lower electrode 10 and theupper electrode 30 have the same polarity, a resistance of the MTJbecomes low. If the lower electrode has an opposite polarity with theupper electrode 30, the resistance of the MTJ becomes high. Whether theresistance is high or low may indicate whether the data stored in theMJT has the logical value of “0” or “1.”.

FIG. 1A shows an MTJ including the upper electrode 30, and the magneticorientation of the MJT in FIG. 1A is determined based on shapeanisotropy. FIG. 1B describes another MTJ including the upper electrode30 that has a circle shape so that the magnetic orientation ofmagnetization layer is a clockwise or counterclockwise circle.

The lower electrode 10 can be a plug configured to connect the magnetictunnel junction layer 20 to a transistor. The lower electrode 10includes an electric conducting material such as a metal or a metalliccompound.

The upper electrode 30 may include an electric conducting material suchas a metal or a metallic compound.

Further, an MTJ includes stacked layers of a pinned layer, a tunnelbarrier layer, and a free layer. Here, because the detailed structure ofthe MTJ is well known to a person skilled in the art, furtherdescription of the MTJ is omitted.

FIGS. 2A to 2H illustrate a method for forming two MTJs in amagneto-resistive random access memory (MRAM) device in accordance withan embodiment of the present invention.

Referring to 2A, a magnetic tunnel junction layer 120 is deposited onthe lower electrode 110. A photo resist layer (not shown) is depositedon the magnetic tunnel junction layer 120, and a photo resist pattern130 including a hole of a circle shape is deposited over the magnetictunnel junction layer 120 through a lithography process. Referring toFIG. 2A, the magnetic tunnel junction layer 120 is exposed by the holeof the circle shape in the photo resist pattern 130.

In accordance with another embodiment, a photo resist pattern can befabricated to have a cylinder shape. A magnetic tunnel junction layer isdeposited on a lower electrode, and a photo resist layer is formed onthe magnetic tunnel junction layer. Using a lithography process, thephoto resist pattern of cylinder shape can be formed on the magnetictunnel junction layer. In this embodiment, the magnetic tunnel junctionlayer is exposed between the photo resist patterns of cylinder shape.

Here, the photo resist pattern may have a cylinder shape. However, thephoto resist pattern may also have a pillar shape. The flat surface ofthe photo resist pattern may have one shape of a circle, an oval, or apolygon.

Referring to FIG. 2B, a spacer layer 140 is deposited on the magnetictunnel junction layer 120 and the photo resist pattern 130 with auniform thickness through a chemical vapor deposition (CVD) process. Thematerial for the spacer layer 140 may have a high etch selectivity toprevent the loss of the magnetic tunnel junction layer 120 and the upperelectrode 150 during a subsequent process. More specifically, themagnetic tunnel junction layer 120 and an upper electrode 150 have loweretch rates than the spacer layer 140. The spacer layer may include asilicon nitride (SiN), a silicon oxide (SiO), or tungsten (W).

Referring to FIG. 2C, the spacer layer 140 on top of the photo resistpattern 130 and on the magnetic tunnel junction layer 120 at a bottom ofthe hole is removed by an etch-back process performed after the spacerlayer 140 is deposited as shown in FIG. 2B. More specifically, theetch-back process is performed to partially remove the spacer layer 140,until the top surface of the photo resist pattern 130 is exposed and thesurface of the magnetic tunnel junction layer 120 is partially exposedthrough the hole of the circle shape. In this step, a spacer layer 140Ais formed.

Referring to FIG. 2D, the photo resist pattern 130 is removed after theetch-back process. A process for melting down the photo resist pattern130 is performed. If the photo resist pattern 130 is removed, the spacer140A having a circle (or ring) shape remains on the magnetic tunneljunction layer 120.

Referring to FIG. 2E, a metal layer 150 is formed after the photo resistpattern 130 is removed. The metal layer 150 is for forming an upperelectrode of the MTJ. The metal layer 150 is deposited with a uniformthickness on the magnetic tunnel junction layer 120 and the spacer 140A.The metal layer 150 has a different etch selectivity than the spacer140A, which is removed in a subsequent process. The metal layer 150 mayinclude a titanium nitride (TiN) or a tungsten nitride (WN).

Referring to FIG. 2F, the metal layer 150 is partially removed by anetch-back process. Through the etch-back process, the metal layer 150 ontop of the spacer 140A and top of the magnetic tunnel junction layer 120is etched.

Referring to FIG. 2G, the spacer 140A is removed after the etch-backprocess to the metal layer 150. Because the spacer 140A includes amaterial having a higher etch selectivity than the magnetic tunneljunction layer 120 and the metal layer 150, loss of the magnetic tunneljunction layer 120 and the metal layer 150 can be prevented. After thespacer 140A is etched, two upper electrodes 150A concentrically alignedwith each other remain on the magnetic tunnel junction layer 120.

Referring to FIG. 2H, the magnetic tunnel junction layer 120 is etchedusing the two upper electrodes 150A as an etch mask. The two upperelectrodes 150A have a lower etch rate than the magnetic tunnel junctionlayer 120 so that loss of the two upper electrodes 150A can beprevented. To achieve a proper etch rate during this etching process, anetching gas is properly selected. To etch the magnetic tunnel junctionlayer 120, the etching gas may include one or more materials of CH₃OH,CO, NH₃, Cl₂, SF₆, and NF₃.

FIG. 3 illustrates an MRAM including a plurality MTJ in accordance withan embodiment of the present invention.

As shown in FIG. 3, a unit memory cell includes a plurality of MTJs 210and a transistor 220, which is coupled to a bit line 230, a source line240, and a word line 250. The plural MTJs 210 are commonly connected toa single transistor 220. Because the unit memory cell includes theplurality of MTJs 210 so that multi-bit data can be stored in a singleunit cell, integration of MRAM can be increased. The plurality of MTJs210, concentrically aligned with each other, respectively have differenttunneling characteristics. In a plane view, the plural MTJs may have ashape of a circle, an oval, or a polygon.

In a unit memory cell according to an embodiment of the presentinvention, a lower electrode includes one selected from the group of TiNand TaN, and an upper electrode includes one selected from the group ofTiN and WN.

In a write operation, a write current supplied through the bit line 230and the source line 240 has an influence on polarities of the pluralityof MTJs 210 so that logical data based on the polarities are stored.Similarly, in a read operation, a read current passing through theplurality of MTJs 210 flows between the bit line 230 and the source line240 so that logical data can be recognized based on a voltage gapbetween the bit line 230 and the source line 240.

FIG. 4 illustrates the MTJ manufactured by the method shown in FIGS. 2 ato 2 h.

Referring to FIG. 4, over a lower electrode, a plurality of MTJs, eachbeing a concentrically aligned and having a circle shape, are formed.The plurality of MTJs may be formed to a circle shape. In anotherembodiment, the plurality of MTJs may be formed in the shape of acircle, oval, and polygon in a plane view.

As discussed earlier, in accordance with embodiments of the presentinvention, by connecting a plurality of magnetic tunnel junctions inparallel, multi-bit data can be stored in a single storage element.Further, integration and operation speed of the non-volatile MRAM can beimproved.

While the present invention has been described with respect to thespecific embodiments, it will be apparent to those skilled in the artthat various changes and modifications may be made without departingfrom the spirit and scope of the invention as defined in the followingclaims.

1. A method for manufacturing a semiconductor memory device, comprising:forming a magnetic tunnel junction layer on a lower electrode; forming aspacer having an annular shape on the magnetic tunnel junction layer;forming upper electrodes on both sidewall surfaces of the annular shapedspacer; removing the spacer; and etching the magnetic tunnel junctionlayer by using the upper electrodes as an etch mask.
 2. The method asrecited in claim 1, wherein the forming of the spacer having an annularshape comprises: forming a photo resist pattern having a hole on themagnetic tunnel junction layer; forming a layer on a top surface andboth sidewalls the photo resist pattern and on the exposed magnetictunnel junction layer in the hole; removing a part of the layer arrangedon the magnetic tunnel junction layer and on the top surface of thephoto resist pattern; and removing the photo resist pattern.
 3. Themethod as recited in claim 1, wherein the forming of the spacer havingan annular shape includes: forming a photo resist pattern having apillar shape on the magnetic tunnel junction layer; forming a layer on atop surface and both sidewalls the photo resist pattern and on theexposed magnetic tunnel junction layer; removing a part of the layerarranged on the magnetic tunnel junction layer and on the top surface ofthe photo resist pattern; and removing the photo resist pattern.
 4. Themethod as recited in claim 1, wherein the forming of the upperelectrodes includes: forming a metal layer on a top surface and bothsidewall surfaces the spacer and the exposed magnetic tunnel junctionlayer; removing a part of the metal layer arranged on the magnetictunnel junction layer and a top surface of the spacer to form the upperelectrodes; and removing the spacer.
 5. The method as recited in claim1, wherein the spacer, the magnetic tunnel junction layer, and the upperelectrode have different etching selectivity.
 6. The method as recitedin claim 5, wherein the spacer includes at least one selected from thegroup of SiN, SiO, and tungsten (W).
 7. The method as recited in claim1, wherein the upper electrodes has a lower etch rate than the magnetictunnel junction layer.
 8. The method as recited in claim 7, wherein theupper electrodes includes one selected from the group of TiN and WN. 9.The method as recited in claim 1, wherein the lower electrode includesat least one selected from the group of TiN and TaN.
 10. The method asrecited in claim 1, wherein the spacer includes a plurality of patternedspacers, each patterned spacers having a concentric circle-shape, andthe upper electrodes are arranged on both surfaces of the plurality ofpatterned spacers.
 11. A semiconductor memory device, comprising: aplurality of magnetic tunnel junction elements configured to store data;and a transistor commonly connected to the plurality of magnetic tunneljunctions, wherein the plurality of magnetic tunnel junction elementsincludes a plurality of concentrically aligned magnetic tunnel junctionlayers and plurality of concentrically aligned upper electrodes over alower electrode,
 12. The semiconductor memory device as recited in claim11, wherein the plural magnetic tunnel junction layers have one shapeselected from the group of circle, oval, and polygon.
 13. Thesemiconductor memory device as recited in claim 11, wherein the pluralmagnetic tunnel junction elements respectively have different tunnelingcharacteristics.
 14. The semiconductor memory device as recited in claim11, wherein the upper electrode includes at least one selected from thegroup of TiN and WN.
 15. The semiconductor memory device as recited inclaim 11, wherein the lower electrode includes at least one selectedfrom the group of TiN and TaN.
 16. The semiconductor memory device ofclaim 11, wherein the plurality of concentrically aligned magnetictunnel junction layers and plurality of concentrically aligned upperelectrodes are annular shaped.
 17. The semiconductor memory device ofclaim 11, wherein the transistor is coupled to a bit line, a sourceline, and a word line.